1. Field of the Invention
The present invention relates to a logic circuit, an amplifier circuit or the like that is provided with a switching transistor isolating a power source.
2. Description of the Related Art
In recent years, there has been a request for a portable electronic device, which operates at higher speed, and also which is driven for a longer time by a battery. For the purpose of responding to the request, there is a demand for a semiconductor integrated circuit to be mounted on such portable electronic devices, which achieves low power consumption while capable of operating at a high speed. When a power source voltage of a semiconductor integrated circuit is reduced for the purpose of reducing power consumption, an operating speed of the semiconductor integrated circuit is also reduced. Accordingly, it is necessary to reduce a threshold voltage (Vth) of a MOS transistor (also termed as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)). When the threshold voltage of the MOS transistor is reduced, a leakage current is increased. For this reason, in the case of a MT-CMOS (Multi Threshold-Complementary Metal Oxide Semiconductor) technique that uses a several kinds of threshold voltages, a transistor having a high threshold voltage (High Vth) serving as a switching transistor is disposed between an actual power source line and a power source line of a circuit formed of a transistor having a low threshold voltage (Low Vth). Thereby, electric power can be controlled (see, for example, Japanese Patent Application Laid-open No. 2004-186666, pp. 19, FIGS. 1, 2).
However, in a semiconductor integrated circuit, which has a leakage current cut-off circuit, and which is formed by the MT-CMOS technique, there is a problem as follows. Specifically, it is necessary to form a cell having a leakage current cut-off circuit inserted thereinto in a circuit formed of a low threshold voltage transistor each time. As a result, a time required for designing a layout of the semiconductor integrated circuit is increased. In addition, the size of a cell having a leakage current cut-off circuit inserted thereinto becomes larger than that of an existing basic cell. This causes a problem where the number of cell libraries is increased because it is necessary to create a new cell library as a MT-CMOS cell having a leakage current cut-off circuit inserted thereinto.